Implement simple CPU in VHDL homework help

Implement simple CPU in VHDL

ROM A Read only Memory should contain the instructions. Your program should go here. Debounce circuit A debounce circuit should be included in your code but not used. Microprocessor Control This is implemented using a Finite State Machine. It should be split into a combinatorial always block and a sequential always block. The combinatorial always block determines the next state of the controller. In the state where it executes the command it should contain a case statement on the opcode. The sequential always block should determine the current state from the next state, increment the program counter, and execute jumps. All module calls should be done using association by position, rather than association by name. Code must be done in System Verilog, and always blocks should be always_comb, and always_ff. There should be no inferred latches. Initialize all variables set in every always statements in every module during reset. Run reset first thing in the test bench. Execute reset before using the programmed FPGA. Block Description

1. The Program Counter (PC) provides the address for the instruction to be executed. It should be incremented (PC=PC+1) in the “Write Back” cycle to point to the next instruction in the Instruction Memory (IM). But, if the current instruction is a JMP instruction, the PC will be updated during the

2. The Instruction Memory is a 16-bit wide ROM with 256 locations. It outputs the instruction pointed to by the PC.

3. The Instruction Register latches the value being output from the Instruction Memory during the Instruction Fetch Cycle. It contains four fields as indicated in the above diagram. OPCODE indicates which instruction is to be executed. RA points to a location in the register file to be used as data or, in the case of the LDI instruction, contains the immediate data used by that instruction. RB points to a location in the register file to be used as data or, in the case of the LDI and ADI instructions, contains the immediate data used by those instructions. RD points to the location in the register file to which results will be written by those instructions which need to store a result.

4. The Register File is a three-ported memory which contains 16 8-bit values. The three ports consist of two read ports which are addressed by RA and RB and can be read simultaneously during the Instruction Decode cycle. The third port is a write port addressed by RD and is written to in the Write Back cycle.

5. The ALU is a logic block that takes data from any of four inputs and outputs a result as indicated by the opcode (see Table 2).

6. The W Register is a single 8-bit register that latches the results of the ALU operation during the Execute Cycle.

Step 2: Switches, LEDs, 7-segment Display and other board specifics should be as follows:

1. SW0 should be used as the asynchronous active-high reset signal. When on, you should be in reset (FSMs should start in their reset state and you should clear the contents of the register file on reset).

2. CLOCK: The clock used for your state machine(s) should be the internal 50MHz clock (PIN_M9), BUT see the next instruction regarding single-step mode.

3. SW1 will be used as a single-step mode switch. If SW1 is off, then once we come out of reset our microprocessor will execute whatever sequence exists in the ROM until it reaches a HALT instruction. If SW1 is on, we will be in single-step mode. In this mode, the microprocessor will stop at the end of every EXECUTE cycle so that we can monitor various contents of the microprocessor as specified below.

4. KEY0 will be used as the single-step advance button. This means that when in single-step mode (that is, SW1 is high) every time we push KEY0 we will advance to the next instruction.

5. The 8 lowest LEDs (LED [7:0]) should normally indicate the address of the current instruction, which is the value stored in the PC. That is, if we are executing the instruction at 8’b00011010, then the LEDs should display off-off-off-on-on-off-on-off. This is the default for LED [7:0].

6. {KEY3,KEY2,KEY} will be used to select which output goes to the 7-segment display based on this table. Align the display to the right using the number of segments required for the desired display

For “display name” display your last name (up to 4-letters only). You will need to press these buttons in combinations. Solution

WREG.sv

module WREG(input CLK,inputLD,input [7:0] IN,output logic [7:0] OUT);

always_ff @(posedge CLK)

if(LD)

OUT <= IN;

endmodule

IR.sv

// instruction register

module IR(input CLK,inputLD,input [15:0] IN,output logic [15:0] OUT);

always_ff @(posedge CLK)

if(LD)

OUT <= IN;

endmodule

MUX0_8.sv

module MUX0_8(input [7:0] A,inputSEL,output [7:0] C);

and G0(C[0],SEL,A[0]);

and G1(C[1],SEL,A[1]);

and G2(C[2],SEL,A[2]);

and G3(C[3],SEL,A[3]);

and G4(C[4],SEL,A[4]);

and G5(C[5],SEL,A[5]);

and G6(C[6],SEL,A[6]);

and G7(C[7],SEL,A[7]);

endmodule

FA1.sv

// full adder 1 bit

module FA1(input A,B,CIN, output S,COUT);

wire XOR1,AND1,AND2;

xor G1(XOR1,A,B);

and G2(AND1,A,B);

xor G3(S,XOR1,CIN);

and G4(AND2,XOR1,CIN);

or G5(COUT,AND1,AND2);

endmodule

REG_FILE.sv

module REG_FILE(input CLK,input [3:0] RA,RB,RD,inputWR,input [7:0] D,output logic [7:0] A,B);

reg [7:0] MEM [0:15];

always_ff @(posedge CLK)

if (WR)

MEM[RD] <= D;

always_comb

begin

A<=MEM[RA];

B<=MEM[RB];

end

endmodule

PC.sv

module PC(input CLK,inputRST,inputJMP,input [7:0] JADDR,INC,output logic [7:0] PCNXT);

wire [7:0] PCINC;

wire N,Z,C,O;

ADDSUB8 G0(PCNXT,INC,1’b0,PCINC,N,Z,C,O);

always_ff @(posedge CLK)

begin

if (RST) PCNXT <= 8’h00;

else if (JMP) PCNXT <= JADDR;

else PCNXT <= PCINC;

end

endmodule

DIV8.sv

module DIV8(input [7:0] A,B,output logic [7:0] D);

reg [15:0] dividend_copy, divider_copy, diff;

integer i;

always_comb begin

D = 0;

dividend_copy = {8’d0,A};

divider_copy = {1’b0,B,7’d0};

for (i=8; i>=1; i=i-1)

begin

diff = dividend_copy – divider_copy;

D = D << 1;

if( !diff[15] ) begin

dividend_copy = diff;

D[0] = 1’d1;

end

divider_copy = divider_copy>> 1;

end

end

endmodule

ROM.sv

module ROM(input [7:0] ADDR,output logic [15:0] DATA);

always_comb

case (ADDR)

8’h00: DATA = 16’h1000;

8’h01: DATA = 16’h1011;

8’h02: DATA = 16’h1002;

8’h03: DATA = 16’h10A3;

8’h04: DATA = 16’hF236;

8’h05: DATA = 16’h2014;

8’h06: DATA = 16’h3100;

8’h07: DATA = 16’h3401;

8’h08: DATA = 16’h8022;

8’h09: DATA = 16’hC040;

8’h0A: DATA = 16’h3405;

8’h0B: DATA = 16’hE536;

8’h0C: DATA = 16’hD637;

8’h0D: DATA = 16’h4578;

8’h0E: DATA = 16’h3828;

8’h0F: DATA = 16’h9089;

8’h10: DATA = 16’h909A;

8’h11: DATA = 16’h589B;

8’h12: DATA = 16’h69AC;

8’h13: DATA = 16’h7BCD;

8’h14: DATA = 16’h0000;

default: DATA = 16’h0000;

endcase

endmodule

DEBOUNCER.sv

module DEBOUNCER(input CLK,IN,output OUT);

wire SLOWCLK;

wire Q1,Q2,Q2BAR;

CLKDIV G0(CLK,SLOWCLK);

D_FF G1(SLOWCLK, IN,Q1 );

D_FF G2(SLOWCLK, Q1,Q2 );

assign Q2BAR = ~Q2;

assign OUT = Q1 & Q2BAR;

endmodule

module CLKDIV(input CLK_100M, output reg SLOWCLK);

reg [26:0] COUNTER=0;

always @(posedge CLK_100M)

begin

COUNTER <= (COUNTER>=249999)?0:COUNTER+1;

SLOWCLK <= (COUNTER < 125000)?1’b0:1’b1;

end

endmodule

module D_FF(input DFF_CLOCK, D, output reg Q);

always @ (posedge DFF_CLOCK) begin

Q <= D;

end

endmodule

ADDSUB8.sv

module ADDSUB8(input [7:0] A,B,input SEL, output logic [7:0] S,output logic N,Z,C,O);

wire [7:0] BX,CX,SX;

xor G1(BX[0],B[0], SEL);

FA1 G2(A[0], BX[0],SEL, SX[0],CX[0]);

xor G3(BX[1], B[1], SEL);

FA1 G4( A[1],BX[1],CX[0],SX[1],CX[1]);

xor G5(BX[2], B[2], SEL);

FA1 G6( A[2],BX[2],CX[1],SX[2],CX[2]);

xor G7(BX[3], B[3], SEL);

FA1 G8( A[3],BX[3],CX[2],SX[3],CX[3]);

xor G9(BX[4], B[4], SEL);

FA1 G10( A[4],BX[4],CX[3],SX[4],CX[4]);

xor G11(BX[5], B[5], SEL);

FA1 G12( A[5],BX[5],CX[4],SX[5],CX[5]);

xor G13(BX[6], B[6], SEL);

FA1 G14( A[6],BX[6],CX[5],SX[6],CX[6]);

xor G15(BX[7], B[7], SEL);

FA1 G16( A[7],BX[7],CX[6],SX[7],CX[7]);

always_comb begin

N = SX[7];

Z = ~(SX[0] | SX[1] | SX[2] | SX[3] | SX[4] | SX[5] | SX[6] | SX[7]);

C = CX[7];

O = CX[7] ^ CX[6];

S = SX;

end

endmodule

MUL8.sv

module MUL8(input [7:0] A,B,output [7:0] M);

wire [6:0] M0;

wire [7:0] M1,M2,M3,M4,M5,M6,M7;

wire [7:0] B1,B2,B3,B4,B5,B6,B7;

wire [6:0] N,Z,O;

MUX0_8 G0(B,A[0],{M0,M[0]});

MUX0_8 G1(B,A[1],B1);

ADDSUB8 G2(B1,{M0[6],M0},1’b0,{M1[6:0],M[1]},N[0],Z[0],M1[7],O[0]);

MUX0_8 G3(B,A[2],B2);

ADDSUB8 G4(B2,M1,1’b0,{M2[6:0],M[2]},N[1],Z[1],M2[7],O[1]);

MUX0_8 G5(B,A[3],B3);

ADDSUB8 G6(B3,M2,1’b0,{M3[6:0],M[3]},N[2],Z[2],M3[7],O[2]);

MUX0_8 G7(B,A[4],B4);

ADDSUB8 G8(B4,M3,1’b0,{M4[6:0],M[4]},N[3],Z[3],M4[7],O[3]);

MUX0_8 G9(B,A[5],B5);

ADDSUB8 G10(B5,M4,1’b0,{M5[6:0],M[5]},N[4],Z[4],M5[7],O[4]);

MUX0_8 G11(B,A[6],B6);

ADDSUB8 G12(B6,M5,1’b0,{M6[6:0],M[6]},N[5],Z[5],M6[7],O[5]);

MUX0_8 G13(B,A[7],B7);

ADDSUB8 G14(B7,M6,1’b1,{M7[6:0],M[7]},N[6],Z[6],M7[7],O[6]);

endmodule

MUX2x1_8.sv

module MUX2x1_8(input [7:0] A,B,inputEN,SEL,output [7:0] C);

wire NOTS;

wire [7:0] AND1,AND2,CX;

not G1(NOTS,SEL);

and G2(AND1[0],NOTS,A[0]);

and G3(AND2[0],SEL,B[0]);

or G4(CX[0],AND1[0],AND2[0]);

and G_0(C[0],CX[0],EN);

and G5(AND1[1],NOTS,A[1]);

and G6(AND2[1],SEL,B[1]);

or G7(CX[1],AND1[1],AND2[1]);

and G_1(C[1],CX[1],EN);

and G8(AND1[2],NOTS,A[2]);

and G9(AND2[2],SEL,B[2]);

or G10(CX[2],AND1[2],AND2[2]);

and G_2(C[2],CX[2],EN);

and G11(AND1[3],NOTS,A[3]);

and G12(AND2[3],SEL,B[3]);

or G13(CX[3],AND1[3],AND2[3]);

and G_3(C[3],CX[3],EN);

and G14(AND1[4],NOTS,A[4]);

and G15(AND2[4],SEL,B[4]);

or G16(CX[4],AND1[4],AND2[4]);

and G_4(C[4],CX[4],EN);

and G17(AND1[5],NOTS,A[5]);

and G18(AND2[5],SEL,B[5]);

or G19(CX[5],AND1[5],AND2[5]);

and G_5(C[5],CX[5],EN);

and G20(AND1[6],NOTS,A[6]);

and G21(AND2[6],SEL,B[6]);

or G22(CX[6],AND1[6],AND2[6]);

and G_6(C[6],CX[6],EN);

and G23(AND1[7],NOTS,A[7]);

and G24(AND2[7],SEL,B[7]);

or G25(CX[7],AND1[7],AND2[7]);

and G_7(C[7],CX[7],EN);

endmodule

CONTROL.sv

module CONTROL(input CLK,inputRST,input [3:0] OPCODE,RD,inputN,Z,C,O,output logic [3:0] ALUOP, output logic LD,JMP,WR,INCEN,INCSRC,WROUT);

enum logic [1:0] {F,DE,WB} STATE,NEXT;

always_ff @ (posedge CLK) begin

if (RST) STATE <= F;

else STATE <= NEXT;

end

always_comb begin

NEXT = STATE;

case (STATE)

F: NEXT = DE;

DE: NEXT = WB;

WB: NEXT = F;

default: NEXT = F;

endcase

end

always_comb begin

LD = 1’b0;

JMP=1’b0;

INCSRC=1’b0;

WR =1’b0;

WROUT = 1’b0;

INCEN=1’b0;

case (STATE)

F:

begin

ALUOP = 4’b0000;

LD = 1’b1;

end

DE:

begin

ALUOP = OPCODE;

WROUT = 1’b1;

end

WB:

begin

ALUOP = OPCODE;

INCEN=1’b1;

case (OPCODE)

4’b0000: //halt

INCEN=1’b0;

4’b1011: //nop

begin

JMP=1’b0;

INCSRC=1’b0;

WR =1’b0;

end

4’b1100: //jmp

begin

JMP=1’b1;

INCSRC=1’b0;

WR =1’b0;

end

4’b1111: //cmpj

begin

JMP=1’b0;

WR =1’b0;

INCSRC=~(N ^ O); // use Rd on greater or equal

end

default:

begin

JMP=1’b0;

INCSRC=1’b0;

WR =1’b1;

end

endcase

end

endcase

end

endmodule

ALU.sv

module ALU(input [7:0] A, B, input [3:0] RA, RB, input [3:0] OP, output logic [7:0] OUT,output logic N,Z,C,O);

logic [7:0] A0,B0,RAD,RMUL,RDIV;

logic SEL;

always_comb

case (OP)

4’b0010:

begin

A0=A; //add

B0=B;

SEL=0;

end

4’b0011:

begin

A0=A; //addi

B0={{4{RB[3]}},RB};

SEL=0;

end

4’b0100:

begin

A0=A; //sub

B0=B;

SEL=1;

end

4’b1000:

begin

A0=B; //inc

B0=8’b00000001;

SEL=0;

end

4’b1001:

begin

A0=B; //dec

B0=8’b00000001;

SEL=1;

end

4’b1111:

begin //CMPJ

A0=A;

B0=B;

SEL=1;

end

default:

begin

A0=A;

B0=B;

SEL=0;

end

endcase

ADDSUB8 G0(A0,B0,SEL,RAD,N,Z,C,O);

MUL8 G1(A,B,RMUL);

DIV8 G2(A,B,RDIV);

always_comb

case (OP)

4’b0001: OUT = {RA,RB}; //ldi

4’b0010: OUT = RAD; //add

4’b0011: OUT = RAD; //addi

4’b0100: OUT = RAD; //sub

4’b0101: OUT = A | B; //or

4’b0110: OUT = A & B; //and

4’b0111: OUT = A ^ B; //xor

4’b1000: OUT = RAD; //inc

4’b1001: OUT = RAD; //dec

4’b1010: OUT = ~B; //comp

4’b1011: OUT = A; //nop

4’b1100: OUT = {RA,RB}; //jmp

4’b1101: OUT = RMUL; //mul

4’b1110: OUT = RDIV; //div

default: OUT = A;

endcase

endmodule

uProcessor.sv

// funciton to convert a 4 bit number to a 7 segment display output

function reg [6:0] HEX_DISPLAY(input [3:0] DIGIT);

case (DIGIT)

4’b0000: HEX_DISPLAY = 7’h3f;

4’b0001: HEX_DISPLAY = 7’h06;

4’b0010: HEX_DISPLAY = 7’h5b;

4’b0011: HEX_DISPLAY = 7’h4f;

4’b0100: HEX_DISPLAY = 7’h66;

4’b0101: HEX_DISPLAY = 7’h6d;

4’b0110: HEX_DISPLAY = 7’h7d;

4’b0111: HEX_DISPLAY = 7’h07;

4’b1000: HEX_DISPLAY = 7’h7f;

4’b1001: HEX_DISPLAY = 7’h6f;

4’b1010: HEX_DISPLAY = 7’h77;

4’b1011: HEX_DISPLAY = 7’h7c;

4’b1100: HEX_DISPLAY = 7’h39;

4’b1101: HEX_DISPLAY = 7’h5e;

4’b1110: HEX_DISPLAY = 7’h79;

4’b1111: HEX_DISPLAY = 7’h71;

endcase

endfunction

module uProcessor(input CLK,input RST); //,output [7:0] PCVAL,DO,AA,BB,AO,output [15:0] CURINST, output [2:0] st,output NN,ZZ,CC,OO);

wire [7:0] PCV,DOUT,A,B,ALUOUT,INC;

wire [15:0] INST;

wire [3:0] OPCODE,RA,RB,RD,ALUOP;

wire LD,JMP,WR,INCEN,INCSRC,WROUT;

wire N,Z,O,C;

ROM G0(PCV,INST);

IR G1(CLK,LD,INST,{OPCODE,RA,RB,RD});

CONTROL G2(CLK,RST,OPCODE,RD,N,Z,C,O,ALUOP,LD,JMP,WR,INCEN,INCSRC,WROUT);

REG_FILE G3(CLK,RA,RB,RD,WR,DOUT,A,B);

ALU G4(A,B,RA,RB,ALUOP,ALUOUT,N,Z,C,O);

WREG G5(CLK,WROUT,ALUOUT,DOUT);

MUX2x1_8 G6(8’b01,{{4{RD[3]}},RD},INCEN,INCSRC,INC);

PC G7(CLK, RST, JMP, DOUT, INC, PCV);

endmodule